1. Field of the Invention
The invention relates to a post-CMP wafer clean process, and more particularly to a post CMP wafer clean process to remove particles and slurry from a loafer by a solvent tank with megasonic.
2. Description of the Related Art
Planarization is an important technology in semiconductor process. The surface of the wafer has an even topography during planarization and it is able to prevent from scattering of exposure light source, so that the pattern transfer can be carried out exactly. Planarization technology mainly includes two methods of spin-on glass (SOG) and chemical mechanical polishing (CMP). However, SOG can not satisfy gradually the requirement of planarization as the semiconductor technique enters the field of sub-half-micron. CMP is the only process currently that can provide global planarization in very-large scale integration (VLSI) and ultra-large scale integration (ULSI). CMP in prior art has been used on planarization of shallow trench isolation (STI), inter-layer dielectric (ILD) and inter-metal dielectric (IMD).
CMP is a planarization process to planarize an uneven topography surface by applying mechanical polishing and adding suitable chemical reagent and slurry. When conditional parameters of process can be controlled definitely, 94% even surface can be obtained by CMP. Regarding the post-CMP cleaning processes of the wafer, it includes brush cleaning and spay cleaning to remove the slurry left on the wafer.
FIGS. 1A-1D are illustrating fabrication of metal interconnect in prior art. Referring to FIG. 1A, a dielectric layer 12 having an opening 14, such as contact window or via hole, is formed on a substrate or a conductive layer 10.
Referring to FIG. 1B, a conformal barrier layer 16 including titanium/titanium nitride (Ti/TiN) or titanium nitride (TiN) is formed on the dielectric layer 12. The barrier layer 16 is used to prevent from direct contact of plug in subsequent process and the substrate/conductive layer 10, and also enhance adhesion between the plug, the substrate/conductive layer 10 and the dielectric layer 12. A metal layer 18 such as tungsten is deposited on the barrier layer 16. Since an overhang structure 16a is formed while forming the barrier layer 16, the metal layer 18 can not fill in the opening 14 of FIG. 1A completely and result in a key hole 20 within the metal layer 18.
Referring to FIG. 1C, using the dielectric layer 12 as a stop layer, a portion of the metal layer 18 and barrier layer 16 are removed and the key hole 20 is exposed to result in a dint 20a formed within the metal plug 18a of FIG. 1C. During the step of CMP, slurry 22 and particles are therefore left on the dielectric layer 12 and the dint 20a such that a material layer in subsequent process can not be adhered thereon due to the slurry 22 and particles absorbing moisture easily. The moisture becomes vapor to form a bubble, which is called outgassing, within these layers through a high temperature process of depositing a metal layer subsequently. Outgassing causes the problem of poison via plug and contact plug.
Referring FIG. 1D, the particles and slurry 22 on the dielectric layer 12 are removed. The post-CMP clean process is typically shown in a flow chart of FIG. 2. The process starts from double side scrubber (DSS) 210 after providing a post-CMP wafer 200, and the post-CMP wafer clean process is achieved 220. It is well known to use DSS with ammonium hydroxide (NH.sub.4 OH) and dilute fluoride hydrogen (HF) to remove the slurry residue. However, it is hard for DSS to clean the slurry left on the dint 20a completely. The residual particles and slurry 22 absorb moisture easily during the post-CMP process and the moisture becomes vapor under a high temperature to cause a bubble formed within. The existence of the bubble may cause crack of the conductive layer and short is thus occurred to influence the operation of the device.